Patent · US Expired

Method for testing bus connections of writable and readable integrated electronic circuits, in particular memory components

US6345372B1 · kind B1 · utility

19Cited by

4References

5Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Andreas Dieckmann · Hannover, DE
Markus Donderer · Amberg, DE

Key dates

Filing date	Apr 12, 2000
Grant date	Feb 5, 2002
Priority date	—
Expiry date	Apr 12, 2020

Classification

Technology area (CPC G)Physics
CPC primaryG11C29/10
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A method for testing bus connections of electronic circuits, in particular memory components, selects address and data bit test patterns such that, in a first step of write and read steps, respectively, the bits in the address bit test pattern have a first binary value and, in the first step of write steps, the bits in the data bit test pattern have a second value and, for each following step, starting with the lowest-value or highest-value bit, the respective adjacent bit is assigned a binary value which is complementary to that in the preceding step until, in the final step, all the bits in the address or data bit test pattern have a complementary value.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.