Method and apparatus for a logic circuit design tool
US6345381B1 · kind B1 · utility
14Cited by
20References
35Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 11, 1998 |
| Grant date | Feb 5, 2002 |
| Priority date | — |
| Expiry date | Dec 11, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1006
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A design tool to support design of logic circuits is described. The designer develops a syntax statement that comprises encoded information to a defined syntax governing signal naming, logical function, and circuit performance. The encoded syntax statement describes the desired logical function of the logic circuit and the specific configuration of transistors required to build the logic circuit. The syntax statement is provided to a compiler that processes and decodes the syntax statement, and generates from the syntax statement a behavioral model of the logic circuit and a physical circuit description of the logic circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.