Process for manufacturing MIS transistor with self-aligned metal grid
US6346450B1 · kind B1 · utility
27Cited by
2References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 28, 1999 |
| Grant date | Feb 12, 2002 |
| Priority date | — |
| Expiry date | Jun 28, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
This invention relates to a MIS transistor and its manufacturing process. The process comprises the following steps:a) production of a dummy grid on a substrate, made of a material capable of resisting heat treatment,b) formation of self-aligned source and drain regions on the dummy grid, in the substrate,c) lateral coating of the dummy grid with an electrically insulating layer,d) elimination of the dummy grid and formation of a final grid made of a material with low resistivity, in the same position as the dummy grid.Application to the manufacture of hyper-frequency circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.