Semiconductor device and a process for forming the semiconductor device
US6346469B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 3, 2000 |
| Grant date | Feb 12, 2002 |
| Priority date | — |
| Expiry date | Jan 3, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15787
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Conductive bumps (32) are formed to overlie a semiconductor die (11). The conductive bumps (32) typically have reduced levels of lead, flow at a temperature no greater than 260° C., and have reduced problems associated with alpha particles. In one embodiment, the conductive bump (32) includes a mostly tin (20) with a relatively thin layer of lead (30). The lead (30) and a portion of the tin (20) interact to form a relatively low melting solder close to the eutectic point for lead and tin. Most of the tin (20) remains unreacted and can form a stand off between the semiconductor die (11) and the packaging substrate (42). Other metals and impurities can be used to improve the mechanical or electrical properties of the conductive bumps (32).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.