Modified gate conductor processing for poly length control in high density DRAMS
US6346734B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 4, 1999 |
| Grant date | Feb 12, 2002 |
| Priority date | — |
| Expiry date | Jun 4, 2019 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/90
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a semiconductor substrate having an oxide layer thereon. A gate conductor is provided on the oxide layer, the gate conductor including a layer of polysilicon on the oxide layer, a tungsten silicide layer on the polysilicon layer, and a nitride cap layer on the tungsten silicide layer. The polysilicon layer has a length greater than length of the silicide layer and the nitride layer. Dielectric spacers on the gate conductor overlay the nitride cap layer and the tungsten silicide layer to provide a sidewall substantially flush with the polysilicon layer. Exposed polysilicon on the polysilicon layer is oxidized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.