Input and power protection circuit implemented in a complementary metal oxide semiconductor process using salicides

US6347026B1 · kind B1 · utility

Assignee

• LSI Logic Corporation · US

Inventors

• Roberto Sung · Cupertino, US
• Jau-Wen Chen · Cupertino, US

Key dates

• Filing date: May 26, 1999
• Grant date: Feb 12, 2002
• Expiry date: May 26, 2019

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D89/601

Abstract

Fabricated using a complementary metal oxide semiconductor process including the use of salicides, an input and power protection circuit for use in an integrated circuit protects voltage and signal terminals from both overvoltage and ESD pulses. A diode connected is connected between a first terminal and an inter-transistor node, a field effect transistor is connected between the inter-transistor node and a second terminal, and a lateral bipolar transistor, with a base connected to the inter-transistor node, is connected between the first and the second terminals. When an ESD pulse appears on the first terminal, the voltage at the inter-transistor node increases until a snapback trigger voltage of the field effect transistor is reached whereupon current flows from the first terminal, through the emitter-base junction of the lateral bipolar transistor, through the inter-transistor node, through the field effect transistor, and to the second terminal. In response to the current flow through the inter-transistor node, the lateral bipolar transistor substantially increases the current flow from the first terminal, through the lateral bipolar transistor, and to the second terminal so th…