Jau-Wen Chen
13Patents
4h-index
9Co-inventors
49Inventor score
Filing activity: May 26, 1999 → Mar 30, 2012
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6979869B2 | Substrate-biased I/O and power ESD protection circuits in deep-submicron twin-well process | Electricity | 36 | Expired |
| US6347026B1 | Input and power protection circuit implemented in a complementary metal oxide semiconductor process using salicides | Electricity | 18 | Expired |
| US7582938B2 | I/O and power ESD protection circuits by enhancing substrate-bias in deep-submicron CMOS process | Electricity | 15 | Active |
| US7119405B2 | Implantation method to improve ESD robustness of thick gate-oxide grounded-gate NMOSFET's in deep-submicron CMOS technologies | Electricity | 7 | Expired |
| US7375543B2 | Electrostatic discharge testing | Physics | 3 | Expired |
| US9172241B2 | Electrostatic discharge protection circuit having high allowable power-up slew rate | Electricity | 3 | Active |
| US7317228B2 | Optimization of NMOS drivers using self-ballasting ESD protection technique in fully silicided CMOS process | Electricity | 3 | Expired |
| US8269280B2 | I/O and power ESD protection circuits by enhancing substrate-bias in deep-submicron CMOS process | Electricity | 3 | Active |
| US7763908B2 | Design of silicon-controlled rectifier by considering electrostatic discharge robustness in human-body model and charged-device model devices | Electricity | 3 | Active |
| US7777996B2 | Circuit protection system | Electricity | 1 | Expired |
| US7948036B2 | I/O and power ESD protection circuits by enhancing substrate-bias in deep-submicron CMOS process | Electricity | 1 | Active |
| US7551414B2 | Electrostatic discharge series protection | Electricity | 0 | Active |
| US7379281B2 | Bias for electrostatic discharge protection | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.