System for adjusting clock rate to avoid audio data overflow and underrun
US6347380B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 3, 1999 |
| Grant date | Feb 12, 2002 |
| Priority date | — |
| Expiry date | Mar 3, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11B2020/10814
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A phase locked loop is employed to provide a clock signal for controlling the reading or writing of audio data from or into a memory to avoid memory overflow and underrun. The difference between the write and read pointers is monitored and used for adjusting a divider counter used in the feedback loop of the phase locked loop, by incrementing, decrementing by one or leaving unchanged the value of the counter. The counter is used to divide the output of the phase locked loop to provide a reference signal to the phase locked loop. A reference frequency for reading the audio data may be set close to the writing speed by incrementing or decrementing the reading speed by fine adjustment steps until the reference frequency is reached. After the reference frequency is reached, the reading speed is changed between the reference frequency and a frequency one fine adjustment step away from the reference frequency so that the average reading speed is equal to the writing speed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.