Solder interconnect techniques
US6347901B1 · kind B1 · utility
8Cited by
13References
2Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 1, 1999 |
| Grant date | Feb 19, 2002 |
| Priority date | — |
| Expiry date | Nov 1, 2019 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T403/477
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method and article of fabrication is described featuring a solder layer having a serpentine, interrupted, or interdigitated boundary. The non-planar design of the boundary layer increases the fatigue life of the solder joint by limiting the damage caused by micro-cracking. This irregularity of the solder boundary constrains the propagation of cracks by creating obstacles along the crack path, redirecting the crack away from the intermetallic layer, or by increasing the path along which the crack propagates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.