Method to fabricate a self aligned source resistor in embedded flash memory applications
US6348370B1 · kind B1 · utility
2Cited by
3References
5Claims
0Family size
Assignee
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Key dates
| Filing date | Jul 6, 2000 |
| Grant date | Feb 19, 2002 |
| Priority date | — |
| Expiry date | Jul 6, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/42
Abstract
A method for fabricating a semiconductor resistor in embedded FLASH memory applications is described. In the method a gate array (9) is formed on a semiconductor substrate. Isolations regions (70) are removed and the exposed silicon implanted forming diffused regions (180). The SAS so formed can be configured to function as a resistor element (240).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.