Method of fabricating solder bumps with high coplanarity for flip-chip application
US6348401B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 10, 2000 |
| Grant date | Feb 19, 2002 |
| Priority date | — |
| Expiry date | Nov 10, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K3/3485
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A solder-pump fabrication method is proposed, which is used for the fabrication of solder bumps with high coplanarity over a semiconductor chip for flip-chip application. The proposed solder-bump fabrication method is characterized in the use of a two-step solder-bump fabrication process, including a first step of electroplating solder over UBM (Under Bump Metallization) pads to a controlled height still below the topmost surface of the mask, and a second step of screen-printing solder paste over the electroplated solder layer. The combined structure of the electroplated solder layer and the printed solder layer is then reflowed to form the desired solder bump. Since the proposed solder-bump fabrication method allows the solder material electroplated and printed over the UBM pads to be confined within the mask openings and never exceed the topmost surface of the mask, the resulted solder bumps would not be bridged to neighboring ones. Moreover, the proposed solder-bump fabrication method allows all the resulted solder bumps to be substantially equally sized to achieve high coplanarity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.