Semiconductor device with reduced number of intermediate level interconnection pattern and method of forming the same
US6348408B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 2, 2000 |
| Grant date | Feb 19, 2002 |
| Priority date | — |
| Expiry date | Nov 2, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention also provides a multilevel interconnection structure comprising: at least a set of a first lower level contact plug extending in a lower level inter-layer insulator structure and a first higher level contact plug extending in a higher level inter-layer insulator structure extending over the lower level inter-layer insulator structure, wherein a top of the first lower level contact plug is contact directly with a bottom of the first higher level contact plug without intervening any interconnection pad; a stopper insulating film extending between the lower level inter-layer insulator structure and the higher level inter-layer insulator structure; and at least a lower-level single conductive united structure which further comprises: a second lower level contact plug extending in the lower level inter-layer insulator structure; and a first lower level interconnection extending in a lower-level interconnection groove formed in an upper region of the lower level inter-layer insulator structure, wherein a top surface of the first lower level interconnection is leveled to a top surface of the lower level inter-layer insulator structure and also leveled to the top of t…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.