Recursive decoder architecture for binary block codes
US6349117B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 1, 1998 |
| Grant date | Feb 19, 2002 |
| Priority date | — |
| Expiry date | Jun 1, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/136
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A recursive decoder for decoding a binary codeword of length N having a first stage, at least one intermediate stage, and a final stage. The first stage including a plurality of decoder groups, each of the groups having a plurality of sets of first and second decoders, each of the first and second decoders having a plurality of inputs and an output, a plurality of adder groups, each of the adders having a first input connected to the output of the first decoder of one of the sets and a second input connected to the output of the second decoder of one of the sets, and an output. The at least one intermediate stage including at least one decoder group, each of the at least one decoder group having a plurality of sets of first and second comparators, each of the first and second comparators having inputs and an output, the inputs of each of the comparators in a first intermediate stage connected to the outputs of one of the plurality of adder groups, at least one adder group, each of the adders having a first input connected to the output of the first comparator of one of the sets and a second input connected to the output of the second comparator of one of the sets, and an output, th…
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