CMOS integrated circuit architecture incorporating deep implanted emitter region to form auxiliary bipolar transistor
US6350640B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 18, 1994 |
| Grant date | Feb 26, 2002 |
| Priority date | — |
| Expiry date | Jul 18, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/401
Abstract
To program a CMOS memory, an auxiliary bipolar transistor is formed in a P-well adjacent to the P-well of an NMOS device of the CMOS memory, the auxiliary transistor being capable of forcing a large magnitude current through a fusible link, so as to program the electronic state of the CMOS memory cell into a prescribed binary (1/0) condition. A separate implant mask for the emitter region of the auxiliary transistor allows the geometry and impurity concentration profile of the emitter region to be tailored by a deep dual implant, so that the impurity concentration of the emitter region is not decreased, and yields a reduced base width for the auxiliary transistor to provide a relatively large current gain to blow the fuse, while allowing the doping parameters of the source/drain regions of the CMOS structure to be separately established to prevent thyristor latch-up.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.