Embedded DRAM on silicon-on-insulator substrate
US6350653B1 · kind B1 · utility
149Cited by
11References
9Claims
0Family size
Assignee
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Key dates
| Filing date | Oct 12, 2000 |
| Grant date | Feb 26, 2002 |
| Priority date | — |
| Expiry date | Oct 12, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/0387
Abstract
A semiconductor device is presented which is directed to a method of forming embedded DRAM and logic devices, where the DRAM devices are formed in bulk, single crystalline semiconductor regions and logic devices are formed in silicon-on-insulator (“SOI”) regions and where buried, doped glass is used as a mask to form deep trenches for storage in the bulk region. The resulting structure is also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.