Graded/stepped silicide process to improve MOS transistor
US6350684B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 15, 2000 |
| Grant date | Feb 26, 2002 |
| Priority date | — |
| Expiry date | Jun 15, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/663
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A silicide having variable internal metal concentration tuned to surface conditions at the interface between the silicide and adjoining layers is employed within an integrated circuit. Higher silicon/metal (silicon-rich) ratios are employed near the interfaces to adjoining layers to reduce lattice mismatch with underlying polysilicon or overlying oxide, thereby reducing stress and the likelihood of delamination. A lower silicon/metal ratio is employed within an internal region of the silicide, reducing resistivity. The variable silicon/metal ratio is achieved by controlling reactant gas concentrations or flow rates during deposition of the silicide. Thinner suicides with less likelihood of delamination or metal oxidation may thus be formed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.