MOS-gated device having a buried gate and process for forming same

US6351009B1 · kind B1 · utility

Assignee

• FAIRCHILD SEMICONDUCTOR CORPORATION · US

Inventors

• Christopher Boguslaw Kocon · Mountain Top, US
• Jun Zeng · Torrance, US

Key dates

• Filing date: Mar 1, 1999
• Grant date: Feb 26, 2002
• Expiry date: Mar 1, 2019

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/513

Abstract

An improved trench MOS-gated device comprises a monocrystalline semiconductor substrate on which is disposed a doped upper layer. The upper layer includes at an upper surface a plurality of heavily doped body regions having a first polarity and overlying a drain region. The upper layer further includes at its upper surface a plurality of heavily doped source regions having a second polarity opposite that of the body regions A gate trench extends from the upper surface of the upper layer to the drain region and separates one source region from another. The trench has a floor and sidewalls comprising a layer of dielectric material and contains a conductive gate material filled to a selected level and an isolation layer of dielectric material that overlies the gate material and substantially fills the trench. The upper surface of the overlying layer of dielectric material in the trench is thus substantially coplanar with the upper surface of the upper layer. A process for forming an improved MOS-gate device provides a device whose gate trench is filled to a selected level with a conductive gate material, over which is formed an isolation dielectric layer whose upper surface is substan…