Method for making polycide-to-polycide low contact resistance contacts for interconnections on integrated circuits
US6351037B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 29, 2000 |
| Grant date | Feb 26, 2002 |
| Priority date | — |
| Expiry date | Sep 29, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/32055
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for making interlevel contacts having low contact resistance (Rc) between patterned polycide layers is described. The method and resulting contact structure consists of depositing and conductively doping a first polysilicon layer having a first tungsten silicide (WSi2) layer. The first polysilicon/silicide (first polycide) layer is patterned to form the first polycide inter connecting conducting layer. An insulating layer is deposited over the patterned first polycide layer and contact openings are anisotropically plasma etched in the insulating layer to the underlying polycide layer. The etching is continued to remove completely the first silicide layer in the contact openings, and to etch into the first polysilicon-layer. After a brief hydrofluoric (HF) etch, a second doped polysilicon layer is deposited and patterned to form a second conducting interconnecting level over the contact openings. The second polysilicon-to-first polysilicon interface formed in the contacts results in consistently low contact resistance (Rc). This low Rc is difficult to achieve in the prior art where the second level metallurgy contacts the first tungsten silicide of the first level interconn…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.