Method and apparatus for reducing soft errors in dynamic circuits
US6351151B2 · kind B2 · utility
8Cited by
8References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 18, 2001 |
| Grant date | Feb 26, 2002 |
| Priority date | — |
| Expiry date | Jul 18, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/096
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A technique for reducing soft errors in a dynamic circuit. For one embodiment, a dynamic circuit includes a dynamic logic gate having an output node at which a logical output value of the logic gate is detected. A keeper circuit coupled to the output node is configured to harden the dynamic circuit by increasing the critical charge at the output node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.