Nonvolatile memory device, in particular a flash-EEPROM
US6351413B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 20, 2000 |
| Grant date | Feb 26, 2002 |
| Priority date | — |
| Expiry date | Apr 20, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The memory array comprises a plurality of cells, grouped together in sectors and arranged in sector rows and columns, and has both hierarchical row decoding and hierarchical column decoding. Global word lines are connected to at least two word lines in each sector, through local row decoders; global bit lines are connected to at least two local bit lines in each sector, through local column decoders. The global column decoder is arranged in the center of the memory array, and separates from each other an upper half and a lower half of the memory array. Sense amplifiers are also arranged in the middle of the array, thus saving space. This architecture also provides lesser stress of the cells, better reliability, and better production performance. In addition, each sector is completely disconnected from the remaining sectors, and only the faulty row or column of a single sector should be doubled.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.