Cache coherency mechanism
US6351790B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 16, 1999 |
| Grant date | Feb 26, 2002 |
| Priority date | — |
| Expiry date | Mar 16, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0815
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache coherency mechanism for a computer system having a plurality of processors, each for executing a sequence of instructions, at least one of the processors having a cache memory associated therewith. The computer system includes a memory that provides an address space where data items are stored for use by all of the processors. A behavior store holds in association with an address of each item, a cache behavior identifying the cacheable behavior of the item, the cacheable behaviors including a software coherent behavior and an automatically coherent behavior. When a cache coherency operation is instigated by a cache coherency instruction, the operation is effected dependent on the cacheable behavior associated with the specified address of the item. Methods for modifying the coherency status of a cache are also described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.