Circuit arrangement and method of maintaining cache coherence utilizing snoop response collection logic that disregards extraneous retry responses
US6351791B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 25, 1998 |
| Grant date | Feb 26, 2002 |
| Priority date | — |
| Expiry date | Jun 25, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0831
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing system, circuit arrangement, integrated circuit device, program product, and method improve system response by disregarding extraneous retry signals during the generation of a prioritized response signal from the response signals output from various snooper devices coupled to one another over a shared memory interface. In particular, it has been determined that a subset of retry signals issued by various snooper devices that snoop memory access requests do not have any a bearing upon the ultimate determination of whether or not a particular memory address, or cache line therefor, is stored in any of the snooper devices. As a result, by disregarding these extraneous retry signals, such access requests may be permitted to proceed without having to be reissued, thereby minimizing the time required to process such requests, and eliminating the extraneous traffic that would otherwise be present on the interface. Extraneous retry signals may be disregarded, for example, by prioritizing to a higher relative priority any response signal that indicates that information from a memory address, or cache line therefor, is stored in a single snooper device. As another example, …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.