Translation look-aside buffer for storing region configuration bits and method of operation
US6351797B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 13, 1998 |
| Grant date | Feb 26, 2002 |
| Priority date | — |
| Expiry date | Nov 13, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1027
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
There is disclosed, for use in an x86-compatible processor, a translation look-aside buffer (TLB) that stores region configuration bits (or attribute bits) associated with each physical address stored in the TLB and that makes the region configuration bits available at the same time that the physical address is generated/translated by the TLB. The TLB comprises: 1) a tag array capable of storing an untranslated address in one of N tag entries in the tag array; 2) a data array capable of storing a translated physical address corresponding to the untranslated address in one of N data entries in the data array; and 3) a region configuration array capable of storing region configuration bits associated with the translated physical address in one of N region configuration entries in the region configuration array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.