Merged bipolar and CMOS circuit and method
US6352887B1 · kind B1 · utility
16Cited by
15References
5Claims
0Family size
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Key dates
| Filing date | Mar 25, 1999 |
| Grant date | Mar 5, 2002 |
| Priority date | — |
| Expiry date | Mar 25, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/401
Abstract
A method for fabricating a BiCMOS integrated circuit. The method includes the steps of forming in a single implantation step a base region 211 of a bipolar transistor and a p-well 212 of an n-channel MOS transistor; and forming in a single implantation step a collector contact well 213 of a bipolar transistor and an n-well 208 of a p-channel MOS transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.