Method of manufacturing semiconductor device in which hot carrier resistance can be improved and silicide layer can be formed with high reliability
US6352891B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 17, 1999 |
| Grant date | Mar 5, 2002 |
| Priority date | — |
| Expiry date | Dec 17, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/485
Abstract
The method of manufacturing a semiconductor device having a first and second semiconductor element formation regions. The second gate electrode is of a second semiconductor element formation region while the first semiconductor element formation region is masked. The second source/drain region is a of the second semiconductor element and is formed in the second semiconductor element formation region while the first semiconductor element formation region is masked. The second sidewall insulating film are formed on side portions of the second gate electrode while the first semiconductor element formation regions is masked. The first gate electrode is of a first semiconductor element and is formed in the first semiconductor element formation region while the second semiconductor element formation region is masked. The first source/drain region is of the first semiconductor element and is formed in the first semiconductor element formation region while the second semiconductor element formation region is masked. The first sidewall insulating films is formed on side portions of the first gate electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.