MOSFET with high dielectric constant gate insulator and minimum overlap capacitance
US6353249B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 25, 2001 |
| Grant date | Mar 5, 2002 |
| Priority date | — |
| Expiry date | May 25, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/691
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of fabricating metal oxide semiconductor field effect transistor (MOSFET) devices having a high dielectric constant (k greater than 7) gate insulator, low overlap capacitance (0.35 fF/&mgr;m or below) and a channel length (sub-lithographic, e.g., 0.1 &mgr;m or less) that is shorter than the lithography-defined gate lengths are provided. The methods include a damascene processing step and a chemical oxide removal (COR) step. The COR step produces a large taper on a pad oxide layer which, when combined with a high-k gate insulator, results in low overlap capacitance, sort channel lengths and better device performance as compared to MOSFET devices that are formed using conventional Complementary Metal Oxide Semiconductor (CMOS) technologies.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.