Complex programmable logic device with lookup table
US6353331B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 10, 2000 |
| Grant date | Mar 5, 2002 |
| Priority date | — |
| Expiry date | Jul 10, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17728
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmable logic device (PLD) structure that combines the AND/OR structure of a CPLD with the look-up table (LUT) -based logic structure of a field programmable gate array (FPGA) to implement both wide logic functions and complex logic functions in a single pass. In one embodiment, a CPLD includes a programmable AND array, a programmable OR array, and several look-up tables (LUTs) that are connected to receive product-terms from the programmable AND array and sum-terms from the programmable OR array. The programmable AND array is programmable connected to multiple input lines, and the programmable OR array is programmably connected to receive selected product-terms generated by a group of AND gates of the programmable AND array. Each LUT includes memory cells that are addressed by the sum-term and product-term applied to the LUT input terminals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.