Circuit for converting a logic signal on an output node to a pair of low-voltage differential signals
US6353334B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 27, 2000 |
| Grant date | Mar 5, 2002 |
| Priority date | — |
| Expiry date | Jan 27, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/017545
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Described are a system and method for converting a typical two-level logic signal to a pair of differential logic signals. In accordance with one embodiment, a field programmable gate array (FPGA) is configured to provide a digital signal and its complement on a pair of output terminals. A resistor network connected to these output terminals converts the complementary signals to a pair of differential signals having current and voltage levels within the range established by the LVDS specification. For maximum efficiency, the values of the resistors that make up the resistor network can be selected to match the 100 ohm input resistance exhibited by LVDS receivers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.