Ferroelectric memory device
US6353550B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 13, 2000 |
| Grant date | Mar 5, 2002 |
| Priority date | — |
| Expiry date | Sep 13, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The ferroelectric memory device includes a plurality of memory cells arranged in a matrix at crossings of a plurality of word lines and a plurality of bit lines. Each memory cell includes at least one ferroelectric capacitor composed of a ferroelectric film and first and second electrodes sandwiching the ferroelectric film, a memory cell transistor interposed between the bit line and the first electrode of the ferroelectric capacitor, a cell plate line connected to the second electrode of the ferroelectric capacitor, a reset voltage supply line for supplying a voltage of a potential substantially identical to the potential at the cell plate line, a reset transistor interposed between the reset voltage supply line and the first electrode of the ferroelectric capacitor, and a reset control signal line for controlling ON/OFF of the reset transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.