Method for forming IC's comprising a highly-resistive or semi-insulating semiconductor substrate having a thin, low resistance active semiconductor layer thereon
US6355493B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 30, 2000 |
| Grant date | Mar 12, 2002 |
| Priority date | — |
| Expiry date | Jun 30, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming ICs comprising a highly-resistive or semi-insulating semiconductor substrate having a thin, low resistance active semiconductor layer thereon. In accordance with one embodiment of the method, the entire semiconductor substrate with at least partially prefabricated semiconductor devices disposed thereon is subjected to irradiation sufficient to impart high resistance throughout the substrate and active semiconductor layer. A thin, low resistance, active semiconductor layer is then generated on the substrate body by localized annealing. The (partially) prefabricated semiconductor devices are restored to operability by virtue of the annealing step as defects in the top insulating layers and properties of thin layers underneath the insulator-semiconductor interfaces are “healed.” The annealing step does not, however, heal the defects in the bulk substrate so that it remains semi-insulating. The localized annealing step of the present invention is facilitated as a result of the difference in the thermal stability of radiation-induced defects in the bulk substrate and in the interface regions. Resultant semiconductor integrated circuits have decreased par…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.