Semiconductor package and method for making the same
US6355502B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 25, 2000 |
| Grant date | Mar 12, 2002 |
| Priority date | — |
| Expiry date | Apr 25, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18165
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for making a semiconductor package firstly provides a lead frame having a first surface and a corresponding second surface. The lead frame includes at least a package unit that further includes a die pad, and a plurality of leads disposed on the periphery of the die pad where each of the leads further includes a neck portion. The method then attaches the second surface of the lead frame to a tape, and performs a punching process to cut off the neck portion of the lead so as to form a plurality of conductive blocks disposed independently on the periphery of the die pad. The method further provides a chip having its back surface attach to the first surface of the die pad, and provides electrical connection between the bonding pad and the first surface of the conductive block by using a plurality of bonding wires. Further, the method performs an encapsulating process to encapsulate the chip, the bonding wires, the die pad, and the first surface of the conductive block. The method then performs a singulating process to separate the package unit from the lead frame. Finally the method performs a detaping process to expose the die pad and the second surface of the conductive blo…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.