Asymmetric depletion region for normally off JFET
US6355513B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 25, 2000 |
| Grant date | Mar 12, 2002 |
| Priority date | — |
| Expiry date | Sep 25, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/063
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A semiconductor device efficiently providing the DC currents required in both discrete and integrated circuits operated at low DC supply voltages. The device disclosed in the present invention is an asymmetrical, enhancement mode, Junction Field Effect Transistor (JFET). The device consists of an epitaxial layer on the surface of a substrate, both of which are doped with the same polarity. The epitaxial layer has a graded doping profile with doping density increasing with distance from the substrate. A grill-like structure is constructed within the upper and lower bounds of, and extending throughout the length and width of the epitaxial layer, and is doped with a polarity opposite to that of the epitaxial layer. A first electrical connection made to the exposed side of the substrate is defined as the drain electrode. A second electrical connection made to the exposed surface of the epitaxial layer is defined as the source electrode. A third electrical connection made to the grill-like structure is defined as the gate electrode. The asymmetrical, enhancement mode JFET is produced as a three terminal device, with a minimal number of elements and a simplified manufacturing process. Wi…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.