Method of manufacturing a mask ROM bit line
US6355530B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 2, 2000 |
| Grant date | Mar 12, 2002 |
| Priority date | — |
| Expiry date | Aug 2, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B20/00
Abstract
A method of manufacturing a mask ROM. A sacrificial silicon oxide layer is formed on the active region upon the substrate. Patterning the sacrificial silicon oxide layer in order to form a plurality of parallel openings, thereby exposing a portion of the active region. A polysilicon layer is formed on the openings and openings are formed thereon. An ion implantation process is performed on the polysilicon layer. Using a thermal flow process, the ions within the polysilicon layer are driven through the openings into the lower portion of the substrate, thereby forming an ion doping region. The polysilicon layer is etchbacked until the sacrificial silicon oxide layer is exposed. The sacrificial silicon oxide layer is removed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.