Ultra-late programming ROM and method of manufacture
US6355550B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 19, 2000 |
| Grant date | Mar 12, 2002 |
| Priority date | — |
| Expiry date | May 19, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5617
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A ROM embedded in a multi-layered integrated circuit includes rows of transistor memory cells. For reduced area, each transistor in a row optionally shares a terminal with an adjacent transistor in the row, whereby adjacent transistors share one of a source and a drain. A plurality of contact lines, one each connected to each common terminal, serve as address terminals for cells. A plurality of metal layers are connected to the other of the drain or source terminals by filled vias and include a final metal layer defining a metal pad for each of the other terminals. Filled vias couple selected metal pads to selected signal lines to provide “1” outputs from selected cells and signal lines which are not coupled by filled vias to the metal pads provide “0” outputs from selected cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.