Phase lock loop and automatic gain control circuitry for clock recovery
US6356160B1 · kind B1 · utility
18Cited by
4References
36Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 2, 1999 |
| Grant date | Mar 12, 2002 |
| Priority date | — |
| Expiry date | Jul 2, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/033
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A high speed data communication system includes a receiver to recover data and clock signals from communicated data. The receiver circuit has a dual phase lock loop (PLL) circuit. A fine loop of the PLL includes a phase detector providing a differential analog voltage output. Transconductance circuitry converts the differential analog voltage output to a low current analog output. The transconductance circuitry has a variable gain which is controlled by an automatic gain adjust circuit. A coarse loop of the PLL allows for fast frequency acquisition of an internal oscillator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.