Row decoder for a nonvolatile memory with capability of selectively biasing word lines to positive or negative voltages
US6356481B1 · kind B1 · utility
Assignees
Inventors
Key dates
| Filing date | Jun 16, 2000 |
| Grant date | Mar 12, 2002 |
| Priority date | — |
| Expiry date | Jun 16, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The row decoder includes, for each word line of the memory, a respective biasing circuit receiving at the input a row selection signal switching, in preset operating conditions, between a supply voltage and a ground voltage and supplying at the output a biasing signal for the respective word line switching between a first operating voltage, in turn switching at least between the supply voltage and a programming voltage higher than the supply voltage, and a second operating voltage, in turn switching at least between the ground voltage and an erase voltage lower than the ground voltage. Each biasing circuit includes a level translator circuit receiving at the input the row selection signal and supplying as output a control signal switching between the first and the second operating voltages and an output driver circuit receiving as input the control signal and supplying at the output the biasing signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.