Internal regeneration of the address latch enable (ALE) signal of a protocol of management of a burst interleaved memory and related circuit
US6356505B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 31, 2001 |
| Grant date | Mar 12, 2002 |
| Priority date | — |
| Expiry date | Jan 31, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An interleaved memory is readable in a sequential access synchronous mode and in a random access asynchronous mode based upon externally generated command signals including an address latch enabling signal and a chip enable signal. The memory includes a circuit for regenerating the externally generated address latch enabling signal. A first and a second internal replica signal are generated by the circuit. The second internal replica signal has a leading edge that is delayed with respect to a leading edge of the first internal replica signal. A duration of the second internal replica signal is conditionally incremented to prevent non-synchronization between the externally generated address latch enabling signal and the externally generated chip enable signal when the interleaved memory is operating in the sequential access synchronous mode or in the random access asynchronous mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.