Methods and apparatus for using interrupt score boarding with intelligent peripheral device
US6356969B1 · kind B1 · utility
23Cited by
12References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 13, 1999 |
| Grant date | Mar 12, 2002 |
| Priority date | — |
| Expiry date | Aug 13, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, the present invention provides a storage system controller (10) having a main processor (12), a memory (14) and a device interface (18) adapted to interface with a peripheral component (28-32). The controller further includes an interrupt management scoreboard (24) adapted to receive a plurality of writes from the peripheral component(s) prior to interrupting the main processor. The main processor identifies a group of tasks to be executed, and sets up the scoreboard to await the completion of the tasks before interrupting the main processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.