System and method providing cache coherency and atomic memory operations in a multiprocessor computer architecture
US6356983B1 · kind B1 · utility
50Cited by
12References
19Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 25, 2000 |
| Grant date | Mar 12, 2002 |
| Priority date | — |
| Expiry date | Jul 25, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0817
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache coherency directory for a shared memory multiprocessor computer system. A data structure is associated with each cacheable memory location, the data structure comprising locations for storing state values indicating an exclusive state, a shared state, an uncached state, a busy state, a busy uncached state, a locked state, and a pending state. The busy state and pending state cooperate to reserve a cache line for future use by a processor while the cache line is currently being used by one or more other processors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.