Method of forming a squared-off, vertically oriented polysilicon spacer gate
US6358827B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 19, 2001 |
| Grant date | Mar 19, 2002 |
| Priority date | — |
| Expiry date | Jan 19, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/518
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method is taught for forming a rectangular or near rectangular polysilicon sidewall structure, which can be used as an ultra narrow MOSFET gate electrode. The method employs the use a step on a sacrificial oxide against which the polysilicon sidewall is formed. An etch stop, such as a gate oxide is formed alongside the step. A polysilicon layer is deposited over the step followed by a silicon nitride layer. Next a flowable layer is deposited and cured. In a first embodiment the flowable layer is deposited to completely cover the polysilicon layer. Next the wafer is planarized to exposed the polysilicon layer over the high part of the step an to a level wherein the polysilicon/silicon nitride interface is driven away from the step to a distance which determines the final width of the final sidewall structure. The residual flowable layer is then removed and a silicon oxide hardmask is grown over the exposed polysilicon. The polysilicon is anisotropically etched, part way to the through and the hardmask is removed. Anisotropic etching is then continued until the etch stop and the top of the sacrificial oxide are exposed, leaving a polysilicon sidewall with a rectangular cross sectio…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.