Han-Ping Chen
30Patents
8h-index
25Co-inventors
75Inventor score
Filing activity: Dec 13, 1996 → Mar 13, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6358827B1 | Method of forming a squared-off, vertically oriented polysilicon spacer gate | Electricity | 96 | Expired |
| US6285624A | Multilevel memory access method | Physics | 60 | Expired |
| US7153744B2 | Method of forming self-aligned poly for embedded flash | Electricity | 58 | Expired |
| US6649489B1 | Poly etching solution to improve silicon trench for low STI profile | Electricity | 21 | Expired |
| US6828183B1 | Process for high voltage oxide and select gate poly for split-gate flash memory | Electricity | 15 | Expired |
| US6482700B2 | Split gate field effect transistor (FET) device with enhanced electrode registration and method for fabrication thereof | Electricity | 10 | Expired |
| US6569736B1 | Method for fabricating square polysilicon spacers for a split gate flash memory device by multi-step polysilicon etch | Electricity | 9 | Expired |
| US6222211A | Memory package method and apparatus | Electricity | 8 | Expired |
| US10922462B1 | Intellectual property block validation and design integration for integrated circuits | Physics | 7 | Active |
| US6781363B2 | Memory sorting method and apparatus | Emerging Cross-Sectional Technologies | 7 | Expired |
| US9318204B1 | Non-volatile memory and method with adjusted timing for individual programming pulses | Physics | 5 | Active |
| US5972775A | Method of increasing thickness of field oxide layer | Electricity | 5 | Expired |
| US10957394B1 | NAND string pre-charge during programming by injecting holes via substrate | Physics | 4 | Active |
| US11048837B2 | Generation of dynamic design flows for integrated circuits | Physics | 3 | Active |
| US6819593B2 | Architecture to suppress bit-line leakage | Physics | 3 | Expired |
| US6675319B2 | Memory access and data control | Physics | 2 | Expired |
| US11854620B2 | Word line zoned adaptive initial program voltage for non-volatile memory | Electricity | 2 | Active |
| US11139031B1 | Neighbor word line compensation full sequence program scheme | Physics | 2 | Active |
| US10541035B1 | Read bias adjustment for compensating threshold voltage shift due to lateral charge movement | Physics | 2 | Active |
| US10964402B1 | Reprogramming memory cells to tighten threshold voltage distributions and improve data retention | Electricity | 2 | Active |
| US10636501B1 | Memory device with reduced neighbor word line interference using adjustable voltage on source-side unselected word line | Physics | 2 | Active |
| US6125068A | Memory access control | Physics | 1 | Expired |
| US5731625A | Bipolar variable resistance device | Emerging Cross-Sectional Technologies | 1 | Expired |
| US11630930B2 | Generation of dynamic design flows for integrated circuits | Physics | 1 | Active |
| US6849499B2 | Process for flash memory cell | Electricity | 1 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.