Semiconductor device with DMOS and bi-polar transistors
US6359318B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 26, 1999 |
| Grant date | Mar 19, 2002 |
| Priority date | — |
| Expiry date | Feb 26, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/663
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A gate electrode layer is formed opposite to a p type backgate region posed between an n type source region and an n type epitaxial region, with a gate insulating layer interposed therebetween. A sidewall insulating layer is formed to cover a sidewall of the gate electrode layer. A p type backgate region has a relatively shallow p type diffusion region and a relatively deep p type diffusion region. The relatively deep p type diffusion region has a portion overlapping the relatively shallow p type diffusion region, and has its end portion at the substrate surface located directly beneath the sidewall insulating layer. Accordingly, a semiconductor device and a manufacturing method thereof that allow easy control of the threshold voltage of a DMOS transistor and facilitate realization of a rapidly operating bipolar transistor are attained.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.