Method of holding a wafer and testing the integrated circuits on the wafer
US6359457B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | May 17, 1999 |
| Grant date | Mar 19, 2002 |
| Priority date | — |
| Expiry date | May 17, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2831
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A wafer with integrated circuits is held with a holding device having a support surface for the wafer. The support surface is subdivided into at least two segments, each with a temperature influencing device. The temperature of each segment can be set independently to different temperatures. The integrated circuits are tested while thermal contact is made between the wafer and the support surface. Those integrated circuits which are in thermal contact with the first segment are tested while the segment is kept at an essentially constant temperature. The temperature of the second segment is at the same time varied. The second segment is then tested at the changed temperature.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.