Method and apparatus for digital delay locked loop circuits
US6359482B1 · kind B1 · utility
14Cited by
11References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 30, 2000 |
| Grant date | Mar 19, 2002 |
| Priority date | — |
| Expiry date | Aug 30, 2020 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S331/02
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for improving a delay line circuit of a Digital Delay Lock Loop (DDLL) circuit. Each delay stage of the delay line consists of three gates, two NANDs and one inverter. The reduction in the total number of gates decreases the unit delay time for each stage, improving the resolution of each stage of the delay line. In addition, the reduction in the total number of gates in each stage significantly reduces the amount of space necessary for the circuitry of the delay line, resulting in an overall decrease in the size of the DDLL circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.