Methodology for control of short channel effects in MOS transistors
US6362082B1 · kind B1 · utility
164Cited by
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18Claims
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Key dates
| Filing date | Jun 28, 1999 |
| Grant date | Mar 26, 2002 |
| Priority date | — |
| Expiry date | Jun 28, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/116
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of improving short channel effects in a transistor. First, a substance is implanted in a substrate. The substrate is then annealed such that the implanted substance forms at least one void in the substrate. Then, a transistor having a source, a drain, and a channel region is formed on the substrate, wherein the at least one void is in the channel region of the transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.