CMOS latch and register circuitry using quantum mechanical tunneling structures
US6362660B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 13, 2000 |
| Grant date | Mar 26, 2002 |
| Priority date | — |
| Expiry date | Jul 13, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/315
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
CMOS semiconductor latch and register (500) circuitry is disclosed, comprising a first tunneling structure latch circuit (502); data input circuitry (506), coupled and adapted to pass data to (504) said first tunneling structure latch circuit (502), a second tunneling structure latch circuit (514), data transmission circuitry (516), coupled between said first and second tunneling structure latch circuits, and adapted to transfer data from said first tunneling structure latch circuit to said second tunneling structure latch circuit, and data output circuitry (518), coupled to (512) said second tunneling structure latch circuit (514).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.