Output circuit
US6362680B1 · kind B1 · utility
14Cited by
7References
5Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 17, 2000 |
| Grant date | Mar 26, 2002 |
| Priority date | — |
| Expiry date | Oct 17, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M9/00
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An output circuit which can minimize the delay in combining two clocks comprises a multiplexer with a flip flop connected to one input and a clocked latch connected to the other. The clocked latch is transparent during one clocking state so that changes to its input appear directly at its output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.