Method for self-testing integrated circuits
US6363506B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 13, 1999 |
| Grant date | Mar 26, 2002 |
| Priority date | — |
| Expiry date | Apr 13, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318371
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A versatile testing scheme provides both off-line and on-line integrated circuit testing using common test circuitry. The testing scheme generates test patterns, applies test patterns and compacts test responses to test the integrated circuit. The original design of the integrated circuit may be modified so that the functional units of the original design perform test operations during idle processing cycles in the normal mode of operation. To this end, functional units of the design may be constrained to perform the test function by coordinating the generation and application of the test patterns and the compaction of the test responses with a usage profile of the functional units.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.