Dual-damascene process with porous low-K dielectric material
US6365506B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 17, 2001 |
| Grant date | Apr 2, 2002 |
| Priority date | — |
| Expiry date | May 17, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/7682
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
This invention relates to a dual damascene process with porous low-k dielectric material. A first insulating layer is formed on a porous low-k dielectric layer. The first insulating layer has a first pattern for defining a first opening in the low-k dielectric layer. Also, the invention includes the step of forming a second insulating layer on the first insulating layer. Both the first insulating layer and the second insulating layer are used as a hard mask, the two insulating layers being of different materials. The second insulating layer has a second pattern for defining a second opening in the low-k dielectric layer. Then, at least one etch is performed to form a dual damascene structure in the porous low-k dielectric layer by the different insulating layers which cause different protection time in etching the porous low-k dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.