Semiconductor memory storage electrode and method of making
US6365928B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 27, 2000 |
| Grant date | Apr 2, 2002 |
| Priority date | — |
| Expiry date | Jun 27, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/315
Abstract
A storage electrode structure and method of manufacturing thereof. Storage electrodes of dummy cells arranged in a word line direction and a bit line direction at the peripheral regions of a cell are formed such that every two or three dummy cells in a word line direction are formed in a single pattern. As a result, the loading effect produced in the peripheral regions of the cell region is reduced. The invention also reduces short-circuit bridging caused by collapsing storage electrode patterns in the dummy cells since the storage electrodes are not connected together. Accordingly, it is possible to minimize an increase in the loading capacitance of bit lines when an electrical short circuit occurs between a bit line and an associated buried contact.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.